Difference between revisions of "3002"

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3002 is the ND-100 CPU board. It contains the CPU, bus arbitration logic, memory control and other subsystems. It also have the Real time clock and the I/O for the serial console.
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[[Image:ND100-CPU-board.jpg | thumb | ND 100 CPU board]]
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'''3002''' is the [[ND-100]] CPU board. It contains the CPU, bus arbitration logic, memory control and other subsystems. It also has the Real time clock and the I/O for the serial console.
  
There are schematics of the CPU in the NORD-100 Input Output System manual (ND-06.016.01).
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There are schematics of the CPU in the {{ND-doc|06.016.01}}.
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==Switches and indicators==
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As seen from the top, when the card is in the card crate (components on the right hand side).
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console speed thumbwheel switch
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ALD thumbwheel switch
 +
 
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Console speed setting
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* 0 -  110 baud
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* 1 -  150 baud
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* 2 -  300 baud
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* 3 - 2400 baud
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* 4 - 1200 baud
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* 5 - 1800 baud
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* 6 - 4800 baud
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* 7 - 9600 baud
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* 8 - 2400 baud
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* 9 -  600 baud
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*10 -  200 baud
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*11 -  134.5 baud
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*12 -  75 baud
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*13 -  50 baud
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Setting 14 and 15 is not defined (not used?).
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Green LED: CPU self-test OK
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Red LED: CPU self-test NOT OK
  
 
== Description of MOPC ==
 
== Description of MOPC ==
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{{Main|MOPC}}
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[[MOPC]] is the name of the Microprogrammed OPerators Communication, a program stored in the micro code of the CPU. It can be used for low level testing of the hardware.
 
[[MOPC]] is the name of the Microprogrammed OPerators Communication, a program stored in the micro code of the CPU. It can be used for low level testing of the hardware.
 
Whenever the MOPC is active it is communicating via the console connected to the current loop connection on the CPU card.
 
Whenever the MOPC is active it is communicating via the console connected to the current loop connection on the CPU card.
MOPC contains functions for examination of the memory, dumping registers, changing content in registers or memory, controlling breakpoints, bootstrap loading and other things.
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MOPC contains functions for examination of the memory, dumping registers, changing content in registers or memory, controlling breakpoints, [[File_Formats#ND100_Boot_Loaders|bootstrap loading]] and other things.
 
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Main article : [[MOPC]]
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== I/O devices on the CPU board ==
 
== I/O devices on the CPU board ==
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==== RTC IOX register map ====
 
==== RTC IOX register map ====
  
IOX 10:
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;IOX 10
Returns 0 in A register, no other effect.
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:Returns 0 in A register, no other effect.
  
IOX 11:
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;IOX 11
Clears real time counter. This instruction will cause the
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:Clears real time counter. This instruction will cause the next clock pulse to occur exactly 20 ms later.
next clock pulse to occur exactly 20 ms later.
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:If executed often enough it will stop the real-time counter from incrementing. This could affect operators communicating via the console.
If executed often enough it will stop the real-time counter
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from incrementing. This could affect operators communicating
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via the console.
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IOX 12:
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;IOX 12
Read real-time clock status.
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:Read real-time clock status.
  Bit 0=1 : An interrupt will be generated at the next clock pulse.
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: Bit 0=1 : An interrupt will be generated at the next clock pulse.
  Bit 3=1 : A clock pulse has occurred.
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: Bit 3=1 : A clock pulse has occurred.
  Bit 1-2 and 4-15 is always zero.
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: Bit 1-2 and 4-15 is always zero.
  
IOX 13:
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;IOX 13
Set real-time clock status.
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:Set real-time clock status.
  Bit 0=1 : Enable interrupt on next clock pulse.
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: Bit 0=1 : Enable interrupt on next clock pulse.
  Bit 13=1 : Set bit 3 to zero in the real-time clock status word.
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: Bit 13=1 : Set bit 3 to zero in the real-time clock status word.
  
 
=== Console ===
 
=== Console ===
 
 
The console could be disabled by removing a strap.
 
The console could be disabled by removing a strap.
  
 
==== Console IOX register map ====
 
==== Console IOX register map ====
  
IOX 300:
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;IOX 300
Read input data (according to input control word setting).
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:Read input data (according to input control word setting). The last character is transferred to the A register. The data available signal is reset if [[MOPC]] is not active.
The last character is transferred to the A register. The
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data available signal is reset if [[MOPC]] is not active.
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IOX 301:
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;IOX 301
No operation.
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:No operation.
  
IOX 302:
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;IOX 302
Read input status
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:Read input status
  Bit 0=1 : Interrupt on "Data available" enabled.
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: Bit 0=1 : Interrupt on "Data available" enabled.
  Bit 3=1 : Data available. (Never set when [[MOPC]] is active.)
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: Bit 3=1 : Data available. (Never set when [[MOPC]] is active.)
  Bit 4=1 :  
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: Bit 4=1 :  
  Bit 5=1 :  
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: Bit 5=1 :  
  Bit 6=1 :  
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: Bit 6=1 :  
  Bit 7=1 :  
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: Bit 7=1 :  
  
IOX 303:
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;IOX 303
Set input control
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:Set input control
  Bit 0=1 : Enable interrupt on "Data available".
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: Bit 0=1 : Enable interrupt on "Data available".
  Bit 11=0, bit 12=0 : 8 bit data.
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: Bit 11=0, bit 12=0 : 8 bit data.
  Bit 11=1, bit 12=0 : 7 bit data.
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: Bit 11=1, bit 12=0 : 7 bit data.
  Bit 11=0, bit 12=1 : 6 bit data.
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: Bit 11=0, bit 12=1 : 6 bit data.
  Bit 11=1, bit 12=1 : 5 bit data.
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: Bit 11=1, bit 12=1 : 5 bit data.
  Bit 13=0 : 2 stop bits (1.5 stop bits for 5 bit data).
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: Bit 13=0 : 2 stop bits (1.5 stop bits for 5 bit data).
  Bit 13=1 : 1 stop bit.
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: Bit 13=1 : 1 stop bit.
  Bit 14=0 : No parity.
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: Bit 14=0 : No parity.
  Bit 14=1 : Parity bit added to data.
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: Bit 14=1 : Parity bit added to data.
  
IOX 304:
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;IOX 304
Returns 0 in A register, no other effect.
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:Returns 0 in A register, no other effect.
  
IOX 305:
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;IOX 305
Write output data (according to input control word setting).
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:Write output data (according to input control word setting).
  
IOX 306:
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;IOX 306
Read output status.
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:Read output status.
  Bit 0=1 : Interrupt on "Ready for transfer" is enabled.
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: Bit 0=1 : Interrupt on "Ready for transfer" is enabled.
  Bit 3=1 : Ready for transfer.
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: Bit 3=1 : Ready for transfer.
  Bit 1-2 and 4-5 are always zero.
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: Bit 1-2 and 4-5 are always zero ''(should probable be 1-2 and 4-15, an error in the documentation)''.
    (should probable be 1-2 and 4-15, an error in the documentation)
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IOX 307:
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;IOX 307
Set output control.
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:Set output control.
  Bit 0=1 : Enable interrupt on "Ready to transfer"
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: Bit 0=1 : Enable interrupt on "Ready to transfer"
  
Notes :
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=== Notes ===
There is some strange wordings in the manual but I guess that there is
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{{ imbox | text = There is some strange wordings in the manual but one guess is that there is no interrupts or reset of the data ready status bit when MOPC is running.}}
no interrupts or reset of the data ready status bit when MOPC is running.
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== Reference ==
 
== Reference ==
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*{{ND-doc|06.015.02}}
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*{{ND-doc|06.016.01}}
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*{{ND-doc|30.008.3 EN}}
  
Ref. ND-06.015.02 ND-100 Functional Description, 1985
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[[Category:ND-100 hardware]]

Latest revision as of 15:21, 14 January 2018

ND 100 CPU board

3002 is the ND-100 CPU board. It contains the CPU, bus arbitration logic, memory control and other subsystems. It also has the Real time clock and the I/O for the serial console.

There are schematics of the CPU in the Norsk Data Document ND–06.016.01 ND-100 INPUT/OUTPUT SYSTEM .

Switches and indicators

As seen from the top, when the card is in the card crate (components on the right hand side).

console speed thumbwheel switch
ALD thumbwheel switch

Console speed setting

  • 0 - 110 baud
  • 1 - 150 baud
  • 2 - 300 baud
  • 3 - 2400 baud
  • 4 - 1200 baud
  • 5 - 1800 baud
  • 6 - 4800 baud
  • 7 - 9600 baud
  • 8 - 2400 baud
  • 9 - 600 baud
  • 10 - 200 baud
  • 11 - 134.5 baud
  • 12 - 75 baud
  • 13 - 50 baud

Setting 14 and 15 is not defined (not used?).

Green LED: CPU self-test OK

Red LED: CPU self-test NOT OK

Description of MOPC

Main article: MOPC

MOPC is the name of the Microprogrammed OPerators Communication, a program stored in the micro code of the CPU. It can be used for low level testing of the hardware. Whenever the MOPC is active it is communicating via the console connected to the current loop connection on the CPU card. MOPC contains functions for examination of the memory, dumping registers, changing content in registers or memory, controlling breakpoints, bootstrap loading and other things.

I/O devices on the CPU board

The CPU board is equipped with two I/O devices, the real time clock and the system console.

RTC

RTC is the Real-Time Clock. It is a system that could generate interrupts on a 20 ms basis.

RTC IOX register map

IOX 10
Returns 0 in A register, no other effect.
IOX 11
Clears real time counter. This instruction will cause the next clock pulse to occur exactly 20 ms later.
If executed often enough it will stop the real-time counter from incrementing. This could affect operators communicating via the console.
IOX 12
Read real-time clock status.
Bit 0=1 : An interrupt will be generated at the next clock pulse.
Bit 3=1 : A clock pulse has occurred.
Bit 1-2 and 4-15 is always zero.
IOX 13
Set real-time clock status.
Bit 0=1 : Enable interrupt on next clock pulse.
Bit 13=1 : Set bit 3 to zero in the real-time clock status word.

Console

The console could be disabled by removing a strap.

Console IOX register map

IOX 300
Read input data (according to input control word setting). The last character is transferred to the A register. The data available signal is reset if MOPC is not active.
IOX 301
No operation.
IOX 302
Read input status
Bit 0=1 : Interrupt on "Data available" enabled.
Bit 3=1 : Data available. (Never set when MOPC is active.)
Bit 4=1 :
Bit 5=1 :
Bit 6=1 :
Bit 7=1 :
IOX 303
Set input control
Bit 0=1 : Enable interrupt on "Data available".
Bit 11=0, bit 12=0 : 8 bit data.
Bit 11=1, bit 12=0 : 7 bit data.
Bit 11=0, bit 12=1 : 6 bit data.
Bit 11=1, bit 12=1 : 5 bit data.
Bit 13=0 : 2 stop bits (1.5 stop bits for 5 bit data).
Bit 13=1 : 1 stop bit.
Bit 14=0 : No parity.
Bit 14=1 : Parity bit added to data.
IOX 304
Returns 0 in A register, no other effect.
IOX 305
Write output data (according to input control word setting).
IOX 306
Read output status.
Bit 0=1 : Interrupt on "Ready for transfer" is enabled.
Bit 3=1 : Ready for transfer.
Bit 1-2 and 4-5 are always zero (should probable be 1-2 and 4-15, an error in the documentation).
IOX 307
Set output control.
Bit 0=1 : Enable interrupt on "Ready to transfer"

Notes

Reference