ND-100 addressing modes

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The ND-100 series of computers have eight addressing modes. The addressing modes are the same in every CPU model. Every instruction in the ND-100/110/120 CPU is made up of 16 bits. Five bits is op code, three bits the addressing mode and eight bits the displacement. Bit 8 is B relative addressing, bit 9 is indirect addressing and bit 10 is X relative addressing. Combining the three bits gives the eight different addressing modes.

The displacement is the lowest eight bits in the instruction and is used as a two's complement to add to get the effective address.

The resulting address is a 16 bit word. To get the real 24 bit address used to access the physical memory the address is translated by the memory management system. The MMS system is using the normal page table or the alternate page table to translate the address to a physical address.

Symbols used

The following symbols are used for describing the different modes.

ea effective address, the resulting word address
(P) the contents of the program counter
() contents of a register or memory location
d displacement (bit 0-7 of the instruction) as a 2's complement value
n arbitrary address of a memory word
K memory block base address pointer

The following is the mnemonics used to describe the addressing modes.

* the contents of the program counter
,B address relative to B register (pre-indexed)
I indirect address
,X address relative to X register (post-indexed)

P relative addressing

P relative addressing have no mnemonic representation.

ea=(P)+disp

Example:

STA *2

Stores the contents of A-register in the memory two words ahead of the instruction.

B relative addressing

B relative addressing have ,B as mnemonic representation.

ea=(B)+disp

Example:

LDA -4,B

Loads the contents of the memory word pointed on by B-4 into the A-register.

P indirect addressing

P indirect addressing have I as mnemonic representation.

ea=((P)+disp)

Example:

STA I *2

First it reads the word two positions after the instruction and then uses it as the address to store the contents of A-register into memory.

B indirect addressing

B indirect addressing have ,B as mnemonic representation.

ea=((B)+disp)

Example:

STA I 2,B

First it reads the word two positions after the memory position pointed on by B register and then uses it as the address to store the contents of A-register into memory.

X relative addressing

X relative addressing have ,X as mnemonic representation.

ea=(X)+disp

Example:

STA 2,X

The contents of the A-register is stored in the memory cell two words after the memory position pointed on by the X register.

B indexed addressing

B indexed addressing have ,B ,X as mnemonic representation.

ea=(B)+(X)+disp

This addressing mode adds one extra micro cycle to the execution time.

Example:

STA 2,B ,X

The contents of the A-register is stored in the memory cell two words after the memory position pointed on by the X+B registers.

P indirect indexed addressing

P indirect indexed addressing have ,X I as mnemonic representation.

ea=((P)+disp)+(X)

This addressing mode adds one extra memory access to the execution time of the instruction.

Example:

STA ,X I *2

First the contents of the memory two steps after the instruction is read, then the contents of the X-register is added to that value. The resulting address is used for storing the contents of the A-register.

B indirect indexed addressing

B indirect indexed addressing have ,X I ,B as mnemonic representation.

ea=((B)+disp)+(X)

Example:

STA ,X I ,B *2

First the contents of the memory two words after the instruction is read, then the contents of the B register is added to that value. The 16-bit value at the memory location pointed to by that result is added to the contents of the X register. The resulting address is used for storing the contents of the A-register.

References