ND-1xx Instructions: Difference between revisions

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* [[SHA]] – Shift A register
* [[SHA]] – Shift A register
* [[SAD]] – Shift A and D registers connected  
* [[SAD]] – Shift A and D registers connected  
* [[ROT]] –  
===== Types =====
* [[ZIN]] –  
For each shift instruction, one of the following types can be specified
* [[LIN]] –  
:* ''nil (default)'' Arithmetic shift
* [[SHR]] –  
:* [[ROT]] – Rotational shift
:* [[ZIN]] – Zero end input
:* [[LIN]] – Link end input
===== Direction =====
:* ''nil (default)'' Left shift
:* [[SHR]] – Right shift


=== System Control Instructions ===
=== System Control Instructions ===
* [[IOF]] –  
* [[IOF]] – Interrupt system off
* [[ION]] –  
* [[ION]] – Interrupt system on
* [[LWCS]] –  
* [[LWCS]] – Load Writeable Control Store
* [[MON]] –  
* [[MON]] – Monitor Call
* [[PIOF]] –  
* [[PIOF]] –  
* [[PION]] –  
* [[PION]] –  
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*{{ND-doc|06.014|(ND-06.014.02 rev A)}}
*{{ND-doc|06.014|(ND-06.014.02 rev A)}}
*{{ND-doc|99.005|(ND-99.005.02 12/84)}}
*{{ND-doc|99.005|(ND-99.005.02 12/84)}}
[[Category:ND-100 instructions|*]]

Revision as of 23:16, 24 March 2009

Instruction Set

Memory Reference Instructions

Store Instructions

  • STZ – Store zero
  • STA – Store A
  • STT – Store T
  • STX – Store X
  • MIN – Memory increase, skip if zero

Load Instructions

Arithmetic and Logical Instructions

Double Word Instructions

  • LDD – Load double word
  • STD – Store double word

Floating Instructions

  • LDF – Load floating accumulator
  • STF – Store floating accumulator
  • FAD – Add to floating accumulator (C may also be affected)
  • FSB – Subtract from floating accumulator (C may also be affected)
  • FMU – Multiply floating accumulator (C may also be affected)
  • FDV – Divide floating accumulator (Z and C may also be affected)

Byte Instructions

Execute Instruction

  • EXR – Execute instruction found in specified register

Bit Instructions

  • BSKP – Skip next location if specified condition is true
  • BSET – Set specified bit equal to specified condition
  • BSTA – Store and clear K
  • BSTC – Store complement and set K
  • BLDA – load K
  • BLDC – Load bit complement to K
  • BANC – Logical AND with bit complement
  • BORC – Logical OR with bit complement
  • BAND – Logical AND to K
  • BORA – Logical OR to K

Shift Instructions

  • SHT – Shift T register
  • SHD – Shift D register
  • SHA – Shift A register
  • SAD – Shift A and D registers connected
Types

For each shift instruction, one of the following types can be specified

  • nil (default) Arithmetic shift
  • ROT – Rotational shift
  • ZIN – Zero end input
  • LIN – Link end input
Direction
  • nil (default) Left shift
  • SHR – Right shift

System Control Instructions

Transfer Instructions

Load Independent Instructions

Inter-level Instructions

Register Operations

Arithmetic Operations, RAD=1:

C,O,Q may be affected by the following operations

Logical Operations, RAD=0:

Combined Instructions:

Extended Arithmetic Operations:

Floating Conversion

Memory Examine/Deposit Instructions

Sequencing Instructions

Unconditional Jump

Conditional Jump

Skip Instructions

Sources