View source for 3101

'''3101''' is the PIOC interface.
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==Introduction==
PIOC stands for '''Programmable Input Output Controller'''. It is an ND-100 interface card capable of handling four full duplex serial communication lines at up to 800 kbits/s in theory. In practice four duplexlines at 38kbaud is about the limit for the card. The hardware is built around an MC 68000 microprocessor and 128 Kbytes of Random Access Memory (RAM) with error correction logic.

The local memory is mapped into the ND-100 memory map using the thumb wheels at the same way as any memory card. Each step is 128 kbyte and the location of the memory can be read by an [[IOX]] instruction. Reset and halt of the 68000 CPU is controlled from the ND-100 side. The local 8 kbyte EPROM contains reset and interrupt vectors for the local CPU.
In the other direction the PIOC can raise interrupt level 12 

There are several high level protocols handled by the PIOC. For even higher versatility, the PIOC can be programmed in [[PLANC]].

==Switches and indicators==
* thumbwheel 1 - PIOC number switch
* thumbwheel 2 - bank-number switch (least significant)
* thumbwheel 3 - bank-number switch (most significant)
* LED 3 (yellow) - active memory cycle
* LED 1 (red) - MC 68000 reset
* LED 2 (red) - MC 68000 halt

{| class="wikitable"
! PIOC number
! Device number <br> (Octal)
! Ident codes <br> (Octal)
|-
| 0
| 140020
| 140002
|-
| 1
| 140024
| 140003
|-
| 2
| 140030
| 140004
|-
| 3
| 140034
| 140005
|-
| 4
| 140040
| 140006
|-
| 5
| 140044
| 140007
|}

==Connectors==
The A and B connectors are used for I/O, the C connector is used for the [[ND-100 Bus]].

==I/O Devices on the card==
The PIOC is represented to the ND-100 side as one I/O device with two registers.
* PIOC Control word, IOX PIOC+3 (write)
 BIT O = 1 - ENABLE FOR SCIP INTERRUPT
 BIT 2 = 1 — SET ND CALLING INTERRUPT
 BIT 3 = 1 - START OPCOM
 BIT 4 = 1 - RESET
 BIT 5 = 1 - HALT
 BIT 6 = 1 - POWER LOW
 BIT 7 = 1 — SET ND READY INTERRUPT
 BIT 8 = 1 - DISABLE CHECK BIT WRITE
* PIOC Status Word, IOX PIOC+2 (read)
 BIT O = 1 - STATUS CHANGE IN PIOC INTERRUPT ENABLED
 BIT 2 = 1 - STATUS CHANGE IN PIOC (SCIP)
 BIT 4 = 1 - PIOC RESET ON
 BIT 5 = 1 - PIOC HALTED
 BIT 8—15 READS BACK BANK NUMBER OF THE COMMON MEMORY

==See also==
* [[3108]] Expanded PIOC

==References==
*{{ND-doc|02.003.1}}
** [http://www.home.neab.net/ND-library/02-PIOC%20hardware/ND-02.003.01%20PIOC%20Hardware%20Reference%20Manual-Gandalf-OCR.pdf Online pdf of the manual]
** [http://www.home.neab.net/ND-library/02-PIOC%20hardware/ND-02.003.01%20PIOC%20drawings-Gandalf-OCR.pdf Gray scale scans of the drawings]
*{{ND-doc|30.008.3 EN}}, page 233

[[Category:ND-100 hardware]]