ND-110 CPU - Revision history

Gandalf: Added a link to the microcode listing

2019-04-28T11:03:33Z

Added a link to the microcode listing

← Older revision		Revision as of 11:03, 28 April 2019
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	== Microcode format ==		== Microcode format ==
	The ND-110/CX microcode format is described in {{ND-doc\|06.026\|(ND-06.026.01 rev A page 235)}}.		The ND-110/CX microcode format is described in {{ND-doc\|06.026\|(ND-06.026.01 rev A page 235)}}.

			There is a surviving list of the microcode version K <ref name="Microcodelist-K">[http://www.home.neab.net/ND-library/00-Unnumbered/MICROPROGRAMLISTNING%20FOR%20ND-110_32%20BIT%20VERSION%20K-Gandalf-OCR.pdf MICROPROGRAMLISTNING FOR ND-110_32 BIT VERSION K]</ref> in [[Telemuseums storage in Fetsund]]. It's not easy to read and almost 200 pages of code. Interestingly enough, there are some mention of [[SINTRAN IV]] in the code.

	== Reference and Sources ==		== Reference and Sources ==

TArntsen: Typo fix, and capitalise RAM and PROM

2019-01-30T12:01:29Z

Typo fix, and capitalise RAM and PROM

← Older revision		Revision as of 12:01, 30 January 2019
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	* New technology. The CPU is constructed by a gate-array. The CPU concists of three VLSI gate arrays, RMIC, RMAC and BUFALU. The ND-110 CPU is also making extensive usage of programmable logic.		* New technology. The CPU is constructed by a gate-array. The CPU concists of three VLSI gate arrays, RMIC, RMAC and BUFALU. The ND-110 CPU is also making extensive usage of programmable logic.
	* New cache memory strategy. The first micro instruction word of a macroinstruction is stored in cache memory.		* New cache memory strategy. The first micro instruction word of a macroinstruction is stored in cache memory.
	* Address arithmetic. Address arithmetic is performed in the RMAC gate array, not ~~aby~~ the micro code as in ND-100.		* Address arithmetic. Address arithmetic is performed in the RMAC gate array, not by the micro code as in ND-100.
	* The interrupt system. Unlike the ND-100 CPU, the ND-110 (and ND-100/CX) CPU handles synchronous interrupts as traps, in a similar way as [[ND-500]] does.<ref>{{ND-doc\|06.026\|(ND-06.026.01 EN) page 191}}</ref>		* The interrupt system. Unlike the ND-100 CPU, the ND-110 (and ND-100/CX) CPU handles synchronous interrupts as traps, in a similar way as [[ND-500]] does.<ref>{{ND-doc\|06.026\|(ND-06.026.01 EN) page 191}}</ref>
	* The Control Store. The control store is based on fast read/write ~~ram~~ instead of ~~prom~~. At power up the memory is initialised from two 8 kbyte EPROMs. The control store can be read or modified by program.		* The Control Store. The control store is based on fast read/write RAM instead of PROM. At power up the memory is initialised from two 8 kbyte EPROMs. The control store can be read or modified by program.
	* Control logic and timing. Much of the control and timing logic have been moved into PAL chips. The main crystal oscillator is now a 39.3216 MHz oscillator. It is used for the nano-sequencer, the CPU-clock, the bus arbiter, the real time clock and the console UART. The nano-sequencer is a four bit state machine used for timing and control.		* Control logic and timing. Much of the control and timing logic have been moved into PAL chips. The main crystal oscillator is now a 39.3216 MHz oscillator. It is used for the nano-sequencer, the CPU-clock, the bus arbiter, the real time clock and the console UART. The nano-sequencer is a four bit state machine used for timing and control.
	* Power consumption. The power consumption was reduced from 90 watts to 60. {{Citation needed}}		* Power consumption. The power consumption was reduced from 90 watts to 60. {{Citation needed}}

Tingo: /* Introduction */ added a link

2018-04-22T10:19:30Z

Introduction: added a link

← Older revision		Revision as of 10:19, 22 April 2018
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	==Introduction==		==Introduction==
	The ND-110 is an improvement over the ND-100 in a number of areas.		The ND-110 is an improvement over the [[ND-100]] in a number of areas.
	* Size. The CPU, the Memory Management System, cache memory and operator panel processor is combined on one single board.		* Size. The CPU, the Memory Management System, cache memory and operator panel processor is combined on one single board.
	* New technology. The CPU is constructed by a gate-array. The CPU concists of three VLSI gate arrays, RMIC, RMAC and BUFALU. The ND-110 CPU is also making extensive usage of programmable logic.		* New technology. The CPU is constructed by a gate-array. The CPU concists of three VLSI gate arrays, RMIC, RMAC and BUFALU. The ND-110 CPU is also making extensive usage of programmable logic.

Mike: Fixing interrupt system facts. adding links

2010-07-15T18:16:16Z

Fixing interrupt system facts. adding links

← Older revision		Revision as of 18:16, 15 July 2010
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	* New cache memory strategy. The first micro instruction word of a macroinstruction is stored in cache memory.		* New cache memory strategy. The first micro instruction word of a macroinstruction is stored in cache memory.
	* Address arithmetic. Address arithmetic is performed in the RMAC gate array, not aby the micro code as in ND-100.		* Address arithmetic. Address arithmetic is performed in the RMAC gate array, not aby the micro code as in ND-100.
	* The interrupt system. Unlike the ND-100 CPU, the ND-110/CX CPU handles synchronous interrupts as traps, in a similar ~~was~~ as [[ND-500]] does.		* The interrupt system. Unlike the ND-100 CPU, the ND-110 (and ND-100/CX) CPU handles synchronous interrupts as traps, in a similar way as [[ND-500]] does.<ref>{{ND-doc\|06.026\|(ND-06.026.01 EN) page 191}}</ref>
	* The Control Store. The control store is based on fast read/write ram instead of prom. At power up the memory is initialised from two 8 kbyte EPROMs. The control store can be read or modified by program.		* The Control Store. The control store is based on fast read/write ram instead of prom. At power up the memory is initialised from two 8 kbyte EPROMs. The control store can be read or modified by program.
	* Control logic and timing. Much of the control and timing logic have been moved into PAL chips. The main crystal oscillator is now a 39.3216 MHz oscillator. It is used for the nano-sequencer, the CPU-clock, the bus arbiter, the real time clock and the console UART. The nano-sequencer is a four bit state machine used for timing and control.		* Control logic and timing. Much of the control and timing logic have been moved into PAL chips. The main crystal oscillator is now a 39.3216 MHz oscillator. It is used for the nano-sequencer, the CPU-clock, the bus arbiter, the real time clock and the console UART. The nano-sequencer is a four bit state machine used for timing and control.
Line 19:		Line 19:
	== Cache memory details ==		== Cache memory details ==
	In addition to the macro-instruction cache memory also found in the ND-100, the ND-110 had a unique implementation of cache memory on the micro-instruction level. The step known as mapping in the ND-100 was then avoided because the first micro-instruction word of a macro-instruction was written into the control store cache.		In addition to the macro-instruction cache memory also found in the ND-100, the ND-110 had a unique implementation of cache memory on the micro-instruction level. The step known as mapping in the ND-100 was then avoided because the first micro-instruction word of a macro-instruction was written into the control store cache.


	==Versions==		==Versions==
	The ND-110 CPU comes in two versions. A standard version and a fast version. Depending on application the ND-110/CX is 1.5 to 3.5 times faster than ND-110. Both versions comes with memory management, a new type of cache memory and the [[commercial extended instruction set]] as standard.<ref>{{ND-doc\|06.026\|(ND-06.026.01 EN) page 3}}</ref>		The ND-110 CPU comes in two versions. A standard version and a fast version. Depending on application the ND-110/CX is 1.5 to 3.5 times faster than ND-110. Both versions comes with memory management, a new type of cache memory and the commercial extended instruction set as standard.<ref>{{ND-doc\|06.026\|(ND-06.026.01 EN) page 3}}</ref>

	===ND-110===		===ND-110===
	This is the standard ND-110 version. It has the same performance as the [[ND-100/CX]].		This is the standard ND-110 version. It has the same performance as the [[ND-100/CX]].
	It has a 1k word instruction cache and executes with 0.32 Whetstone MIPS.		It has a 1k word instruction cache and executes with 0.32 [[wikipedia:Whetstone (benchmark)\|Whetstone MIPS]].

	===ND-110/CX===		===ND-110/CX===

Gandalf: Added info about cache size in 110 and 110/CX

2009-04-05T00:46:43Z

Added info about cache size in 110 and 110/CX

← Older revision		Revision as of 00:46, 5 April 2009
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	===ND-110===		===ND-110===
	This is the standard ND-110 version. It has the same performance as the [[ND-100/CX]].		This is the standard ND-110 version. It has the same performance as the [[ND-100/CX]].
	It executes with 0.32 Whetstone MIPS.		It has a 1k word instruction cache and executes with 0.32 Whetstone MIPS.

	===ND-110/CX===		===ND-110/CX===
	This is the fast version of the ND-110 CPU. It is 1.5-3.5 faster than the standard version.		This is the fast version of the ND-110 CPU. It is 1.5-3.5 faster than the standard version.
	It executes with 0.55 Whetstone MIPS.		It has a 4k word instruction and data cache and executes with 0.55 Whetstone MIPS.

	==Print versions==		==Print versions==

Gandalf: Added speed comparision

2009-04-02T17:44:02Z

Added speed comparision

← Older revision		Revision as of 17:44, 2 April 2009
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	===ND-110===		===ND-110===
	This is the standard ND-110 version. It has the same performance as the [[ND-100/CX]].		This is the standard ND-110 version. It has the same performance as the [[ND-100/CX]].
			It executes with 0.32 Whetstone MIPS.

	===ND-110/CX===		===ND-110/CX===
	This is the fast version of the ND-110 CPU. It is 1.5-3.5 faster than the standard version.		This is the fast version of the ND-110 CPU. It is 1.5-3.5 faster than the standard version.
			It executes with 0.55 Whetstone MIPS.

	==Print versions==		==Print versions==

Gandalf: More on the difference between standard and /CX

2009-04-02T17:12:39Z

More on the difference between standard and /CX

← Older revision		Revision as of 17:12, 2 April 2009
Line 21:		Line 21:

	==Versions==		==Versions==
	The ND-110 CPU comes in two versions.		The ND-110 CPU comes in two versions. A standard version and a fast version. Depending on application the ND-110/CX is 1.5 to 3.5 times faster than ND-110. Both versions comes with memory management, a new type of cache memory and the [[commercial extended instruction set]] as standard.<ref>{{ND-doc\|06.026\|(ND-06.026.01 EN) page 3}}</ref>

	===ND-110===		===ND-110===
	This ~~was~~ the standard ND-110 version.		This is the standard ND-110 version. It has the same performance as the [[ND-100/CX]].
	In the ~~ND-110 Functional description, appendix E,~~ the ND-~~110 CPU is described as standard speed~~.

	===ND-110/CX===		===ND-110/CX===
	This ~~was~~ the ND-110 ~~with the [[CX microcode PROM]] option~~. ~~The added instructions were the same as the ND~~-~~100/CE {{Citation needed}}~~.		This is the fast version of the ND-110 CPU. It is 1.5-3.5 faster than the standard version.
	In the ~~ND-110 Functional description, appendix E, the ND-110/CX CPU is described as fast speed~~.

	==Print versions==		==Print versions==
Line 73:		Line 71:

	== Reference and Sources ==		== Reference and Sources ==
			<references/>
	*{{ND-doc\|06.026\|(ND-06.026.01 rev A)}}		*{{ND-doc\|06.026\|(ND-06.026.01 rev A)}}

	[[Category:ND-100 hardware]]		[[Category:ND-100 hardware]]

Gandalf: Complete rewrite and added a lot of information. Removing the wikipedia reference.

2009-03-30T19:54:15Z

Complete rewrite and added a lot of information. Removing the wikipedia reference.

← Older revision		Revision as of 19:54, 30 March 2009
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	~~The '''ND-110 CPU''' is an incremental improvement of the [[ND-100 CPU]].~~		{{stub}}

	The ND-110 combined the Memory Management System and CPU, previously separate cards, on one board. The single CPU/MMS board was plugged into the memory management board slot, usually numbered 3. The power consumption was reduced from 90 watts to 60.

	~~The ND-110 made extensive use of PALs and gate arrays - with "semi-custom" VLSI chips.~~

	The ND-110 ~~had~~ three gate arrays:		==Introduction==
			The ND-110 is an improvement over the ND-100 in a number of areas.
			* Size. The CPU, the Memory Management System, cache memory and operator panel processor is combined on one single board.
			* New technology. The CPU is constructed by a gate-array. The CPU concists of three VLSI gate arrays, RMIC, RMAC and BUFALU. The ND-110 CPU is also making extensive usage of programmable logic.
			* New cache memory strategy. The first micro instruction word of a macroinstruction is stored in cache memory.
			* Address arithmetic. Address arithmetic is performed in the RMAC gate array, not aby the micro code as in ND-100.
			* The interrupt system. Unlike the ND-100 CPU, the ND-110/CX CPU handles synchronous interrupts as traps, in a similar was as [[ND-500]] does.
			* The Control Store. The control store is based on fast read/write ram instead of prom. At power up the memory is initialised from two 8 kbyte EPROMs. The control store can be read or modified by program.
			* Control logic and timing. Much of the control and timing logic have been moved into PAL chips. The main crystal oscillator is now a 39.3216 MHz oscillator. It is used for the nano-sequencer, the CPU-clock, the bus arbiter, the real time clock and the console UART. The nano-sequencer is a four bit state machine used for timing and control.
			* Power consumption. The power consumption was reduced from 90 watts to 60. {{Citation needed}}

			== The VLSI chips ==
	* The Micro Instruction Controller, the MIC - also known as RMIC, for "Rask MIC" ("Speedy MIC"). It replaced three 74S482 sequencers and about 30 other ICs.		* The Micro Instruction Controller, the MIC - also known as RMIC, for "Rask MIC" ("Speedy MIC"). It replaced three 74S482 sequencers and about 30 other ICs.
	* The Arithmetical and Logical Unit gate array (ALU, also known as the "BUFALU"). Replaced four Am2901 bit-slice processors, and some additional registers like the data bus register the general purpose register, and the internal register block.		* The Arithmetical and Logical Unit gate array (ALU, also known as the "BUFALU"). Replaced four Am2901 bit-slice processors, and some additional registers like the data bus register the general purpose register, and the internal register block.
	* The Micro Address Controller (The MAC, also called RMAC, for "Rask MAC" ("Speedy MAC"). It implemented hardware address arithmetic, which in the ND-100 had been done in microcode.		* The Micro Address Controller (The MAC, also called RMAC, for "Rask MAC" ("Speedy MAC"). It implemented hardware address arithmetic, which in the ND-100 had been done in microcode.

			== Cache memory details ==
	In addition to the macro-instruction cache memory also found in the ND-100, the ND-110 had a unique implementation of cache memory on the micro-instruction level. The step known as mapping in the ND-100 was then avoided because the first micro-instruction word of a macro-instruction was written into the control store cache.		In addition to the macro-instruction cache memory also found in the ND-100, the ND-110 had a unique implementation of cache memory on the micro-instruction level. The step known as mapping in the ND-100 was then avoided because the first micro-instruction word of a macro-instruction was written into the control store cache.

	~~Unlike the~~ ND-~~100~~ CPU~~, it handled synchronous interrupts as traps, similar to how it was handled by the [[ND-500]]~~.		==Versions==
			The ND-110 CPU comes in two versions.

	~~The control store consisted of 4K x 4 bit 40ns SRAM chips.~~ This ~~meant that~~ the ~~control store was writable~~. ~~It was loaded at power up and Master Clear from two 32Kx8 bit EPROMs~~.		===ND-110===
			This was the standard ND-110 version.
			In the ND-110 Functional description, appendix E, the ND-110 CPU is described as standard speed.

	The CPU ~~clock and the bus arbitration network were implemented using 15ns PALs~~.		===ND-110/CX===
			This was the ND-110 with the [[CX microcode PROM]] option. The added instructions were the same as the ND-100/CE {{Citation needed}}.
			In the ND-110 Functional description, appendix E, the ND-110/CX CPU is described as fast speed.

	~~The main oscillator was a 39.3216 MHz crystal oscillator~~.		==Print versions==
			* [[3090]] An early version of the CPU with two different print release versions (C, K)
			* [[3095]] A later version of the CPU, only known print release version is B.

	==~~=ND-110/CX=~~==		==New instructions ==

	~~This was~~ the ND-~~110~~ with the [[~~CX microcode PROM~~]] ~~option~~. ~~The added instructions were~~ the ~~same as~~ the ND-~~100/CE~~.		* [[TRA]] CS - Reads 16 control storage bits into the A-register. The X-register contains the store address.
			* [[TRR]] CS - Writes the A-register into 16 control store bits. The X-register contains the control store address.
			* [[TRR]] CILP - Cache inhibit individual page.
			* [[VERSN]] - Reads version numbers of print and micro program.
			* [[SETPT]] - Set page tables.
			* [[CLEPT]] - Clear page tables.
			* [[CLNREENT]] - Clear non re-entrant pages.
			* [[CHREENTPAGES]] - Change page tables.
			* [[CLEPU]] - Clear page tables and collect PGU information.
			* [[WGLOB]] - Initialize global pointers.
			* [[RGLOB]] - Examine global pointers.
			* [[INSPL]] - Insert page in page list.
			* [[REMPL]] - Remove page from page list.
			* [[CNREK]] - Clear non re-entrant pages.
			* [[CLPT]] - Clear segment from page tables.
			* [[ENPT]] - Enter segment in page tables.
			* [[REPT]] - Enter re-entrant segment in page tables.
			* [[LBIT]] - Load single bit accumulator (K) with logical memory bit.
			* [[SBITP]] - Store single bit accumulator (K) in a physical memory bit.
			* [[LBYTP]] - Load the A register with a single byte from physical memory.
			* [[SBYTP]] - Store single byte in physical memory.
			* [[TSETP]] - Test and set a physical memory word.
			* [[RDUSP]] - Read a physical memory word without using cache.
			* [[LASB]] - Load the A register with the contents of the segment-table bank (STBNK).
			* [[SASB]] - Store the A register contents in the STBNK.
			* [[LACB]] - Load the A register with the contents of the core map-table bank (CMBNK).
			* [[SACB]] - Store the A register contents in the CMBNK.
			* [[LXSB]] - Load the X register with the contents of the STBNK.
			* [[LXCB]] - Load the X register with the contents of the CMBNK.
			* [[SZSB]] - Store zero in the STBNK.
			* [[SZCB]] - Store zero in the CMBNK.

	{{~~stub~~}}		== Microcode format ==
			The ND-110/CX microcode format is described in {{ND-doc\|06.026\|(ND-06.026.01 rev A page 235)}}.

	== Sources ==		== Reference and Sources ==
	*{{~~OriginWP~~-EN\|~~NORD~~-~~100\|6th February 2009~~}}		*{{ND-doc\|06.026\|(ND-06.026.01 rev A)}}

	[[Category:ND-100 hardware]]		[[Category:ND-100 hardware]]

Mike: Adding link + category

2009-02-13T09:23:45Z

Adding link + category

← Older revision		Revision as of 09:23, 13 February 2009
Line 13:		Line 13:
	In addition to the macro-instruction cache memory also found in the ND-100, the ND-110 had a unique implementation of cache memory on the micro-instruction level. The step known as mapping in the ND-100 was then avoided because the first micro-instruction word of a macro-instruction was written into the control store cache.		In addition to the macro-instruction cache memory also found in the ND-100, the ND-110 had a unique implementation of cache memory on the micro-instruction level. The step known as mapping in the ND-100 was then avoided because the first micro-instruction word of a macro-instruction was written into the control store cache.

	Unlike the ND-100 CPU, it handled synchronous interrupts as traps, similar to how it was handled by the ND-500.		Unlike the ND-100 CPU, it handled synchronous interrupts as traps, similar to how it was handled by the [[ND-500]].

	The control store consisted of 4K x 4 bit 40ns SRAM chips. This meant that the control store was writable. It was loaded at power up and Master Clear from two 32Kx8 bit EPROMs.		The control store consisted of 4K x 4 bit 40ns SRAM chips. This meant that the control store was writable. It was loaded at power up and Master Clear from two 32Kx8 bit EPROMs.
Line 29:		Line 29:
	== Sources ==		== Sources ==
	*{{OriginWP-EN\|NORD-100\|6th February 2009}}		*{{OriginWP-EN\|NORD-100\|6th February 2009}}

			[[Category:ND-100 hardware]]

Gandalf: Initial page copied from wikipedia.

2009-02-07T03:04:50Z

Initial page copied from wikipedia.

New page

The '''ND-110 CPU''' is an incremental improvement of the [[ND-100 CPU]].

The ND-110 combined the Memory Management System and CPU, previously separate cards, on one board. The single CPU/MMS board was plugged into the memory management board slot, usually numbered 3. The power consumption was reduced from 90 watts to 60.

The ND-110 made extensive use of PALs and gate arrays - with "semi-custom" VLSI chips.

The ND-110 had three gate arrays:

* The Micro Instruction Controller, the MIC - also known as RMIC, for "Rask MIC" ("Speedy MIC"). It replaced three 74S482 sequencers and about 30 other ICs.
* The Arithmetical and Logical Unit gate array (ALU, also known as the "BUFALU"). Replaced four Am2901 bit-slice processors, and some additional registers like the data bus register the general purpose register, and the internal register block.
* The Micro Address Controller (The MAC, also called RMAC, for "Rask MAC" ("Speedy MAC"). It implemented hardware address arithmetic, which in the ND-100 had been done in microcode.

In addition to the macro-instruction cache memory also found in the ND-100, the ND-110 had a unique implementation of cache memory on the micro-instruction level. The step known as mapping in the ND-100 was then avoided because the first micro-instruction word of a macro-instruction was written into the control store cache.

Unlike the ND-100 CPU, it handled synchronous interrupts as traps, similar to how it was handled by the ND-500.

The control store consisted of 4K x 4 bit 40ns SRAM chips. This meant that the control store was writable. It was loaded at power up and Master Clear from two 32Kx8 bit EPROMs.

The CPU clock and the bus arbitration network were implemented using 15ns PALs.

The main oscillator was a 39.3216 MHz crystal oscillator.

===ND-110/CX===

This was the ND-110 with the [[CX microcode PROM]] option. The added instructions were the same as the ND-100/CE.

{{stub}}

== Sources ==
*{{OriginWP-EN|NORD-100|6th February 2009}}