ND-120 CPU - Revision history

RHansen: Updated info on RTC chip and function of 68705 cpu

2024-02-10T11:58:04Z

Updated info on RTC chip and function of 68705 cpu

← Older revision		Revision as of 11:58, 10 February 2024
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	** In the ND-120 the CPU is constructed from one big VLSI gate array, the CPU Gate Array (CGA)		** In the ND-120 the CPU is constructed from one big VLSI gate array, the CPU Gate Array (CGA)
	*** The ND-120 has a helper chip, the DELILAH Decoding Logic Gate Array (DGA). It was produced by NEC.		*** The ND-120 has a helper chip, the DELILAH Decoding Logic Gate Array (DGA). It was produced by NEC.
	** There is an onboard 68705U3 CPU/Microcontroller on the CPU board~~, for Panel Control~~ and ~~real-time clock~~.		** There is an onboard 68705U3 CPU/Microcontroller on the CPU board and an MM58274 Real Time Clock (RTC) chip with a battery backup.
			*** Preliminary analysis of the PROM code seem to indicate it replaces the 'Days' and 'Seconds' Read/Write logic normally send to the external Panel Controller
	* Cycle Control:		* Cycle Control:
	** The cycle controller, which defines the timing sequence in executing microinstructions, operates differently in the ND-120 compared to the ND-110.		** The cycle controller, which defines the timing sequence in executing microinstructions, operates differently in the ND-120 compared to the ND-110.

RHansen: /* Overview */

2024-02-10T11:46:07Z

Overview

← Older revision		Revision as of 11:46, 10 February 2024
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	==Overview==		==Overview==
	The ND-120/CX CPU was a complete reimplementation on an LSI chip (The so-called Delilah chip).		The ND-120/CX CPU was a complete reimplementation on an LSI chip (The so-called Delilah chip).

	The RMIC, RMAC and ALU chip on the ND-110 was integrated into one LSI chip together with the interrupt handling that had been done using two AMD 2914 chips.		The RMIC, RMAC and ALU chip on the ND-110 was integrated into one LSI chip together with the interrupt handling that had been done using two AMD 2914 chips.

RHansen: Added details about RMIC,RMAC, ALU, Interrupt

2024-02-10T11:45:45Z

Added details about RMIC,RMAC, ALU, Interrupt

← Older revision		Revision as of 11:45, 10 February 2024
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	==Overview==		==Overview==
	The ND-120/CX CPU was a complete reimplementation on an LSI chip (The so-called Delilah chip).		The ND-120/CX CPU was a complete reimplementation on an LSI chip (The so-called Delilah chip).
			The RMIC, RMAC and ALU chip on the ND-110 was integrated into one LSI chip together with the interrupt handling that had been done using two AMD 2914 chips.

	The designers was Lasse Bockelie and Chris Cherrington.		The designers was Lasse Bockelie and Chris Cherrington.


	==Introduction==		==Introduction==

Tingo: add it to the category ND-100 hardware

2023-12-26T14:31:56Z

add it to the category ND-100 hardware

← Older revision		Revision as of 14:31, 26 December 2023
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	The ND-120 CPU was a complete reimplementation on an LSI chip (The so-called Delilah chip).		The ND-120 CPU was a complete reimplementation on an LSI chip (The so-called Delilah chip).
	This is part 2 of 2 - with Chris Cherrington from February 1987		This is part 2 of 2 - with Chris Cherrington from February 1987

			[[Category:ND-100 hardware]]

RHansen: added 3202 link

2023-12-22T03:53:05Z

added 3202 link

← Older revision		Revision as of 03:53, 22 December 2023
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	==Introduction==		==Introduction==
	The ND-120/CX is an improvement over the [[ND-110_CPU]] in a number of areas.		The ND-120/CX is an improvement over the [[ND-110_CPU]] in a number of areas.
	* Finally, the CPU board has an UART with RS-232 interface. Up until now all the ND CPU's used current-loop interface.		* Finally, the [[3202]] CPU board has an UART with RS-232 interface. Up until now all the ND CPU's used current-loop interface.
	* Onboard memory up to 6MB.		* Onboard memory up to 6MB.
	* The ND-120/CX CPU is a high-speed version (approximately 1.9 times faster) of the ND-110/CX CPU.		* The ND-120/CX CPU is a high-speed version (approximately 1.9 times faster) of the ND-110/CX CPU.

RHansen: First summary of the great ND-120/CX CPU

2023-12-22T03:51:27Z

First summary of the great ND-120/CX CPU

New page

{{stub}}

==Overview==
The ND-120/CX CPU was a complete reimplementation on an LSI chip (The so-called Delilah chip).

The designers was Lasse Bockelie and Chris Cherrington.

==Introduction==
The ND-120/CX is an improvement over the [[ND-110_CPU]] in a number of areas.
* Finally, the CPU board has an UART with RS-232 interface. Up until now all the ND CPU's used current-loop interface.
* Onboard memory up to 6MB.
* The ND-120/CX CPU is a high-speed version (approximately 1.9 times faster) of the ND-110/CX CPU.
* The ND-120 CPU is upwards compatible with the ND-110 and ND-100 CPUs.
* The CPU
** In the ND-110 the CPU is constructed from three VLSI gate arrays (RMIC, RMAC and BUFALU).
** In the ND-120 the CPU is constructed from one big VLSI gate array, the CPU Gate Array (CGA)
*** The ND-120 has a helper chip, the DELILAH Decoding Logic Gate Array (DGA). It was produced by NEC.
** There is an onboard 68705U3 CPU/Microcontroller on the CPU board, for Panel Control and real-time clock.
* Cycle Control:
** The cycle controller, which defines the timing sequence in executing microinstructions, operates differently in the ND-120 compared to the ND-110.

* Microcache:
** The ND-110 has a 2K long instruction cache and microcache address area occupying the top 2K in control store.
** The ND-120, in contrast, has a 1K long instruction cache and microcache address area occupying the top 1K in control store.
** In ND-120, the address range 6—7K is not required for microcache, and may be used as a further 1K of extension area.

==Print versions==
* [[3202]] - The development phase used board revisions A, B and C
* [[3202]] - The final revision was D. The design documents dates this revision to 5/10/1987.

==Macrocode==
There doesnt seem to be any new macrocode opcodes in the ND-120/CX vs the ND-110/CX.

==Microcode==
The microcode is very similar to the microcode in the [[ND-110]] except a few changes.
And most of the changes seems to be related to the change of the UART.

Summary:
* For the ND-110, bits 21-27 of the microinstruction word are inverted after assembly. This has been fixed for the ND-120.
* Bit 21 has been renamed to DLY from DELAY to accord with revised timing delay function.
* Bits 32-36 ('''Command''' field):
** Changed '''Command 5'''
*** In ND-110, 'RSDA' - Reset the data available signal from UART.
*** In the ND-120, the command 'CEUART' depends on the value in MIS field (MIS1 and MIS0)
**** 05,0 - UART data (r/w data)
**** 05,1 - UART status (r/w status)
**** 05,2 - UART mode (r/w mode)
**** 05,3 - UART comm (r/w comm)
**** See the datasheet on the 2661 UART device for further details:
***** https://datasheetspdf.com/pdf-file/1412058/SMSC/COM2661-3/1
***** https://bitsavers.org/components/microchipTechnology/_dataBooks/1990_Microchip_Data_Book.pdf
** New '''Command 36.2''' : LCS (Load Command Store) - The whole of the control store is loaded from Control Store PROM to Control Store RAM
** New '''Command 36.3''' : XSLOW - In ND-120, force current microcycle to the maximum length of time (435.2ns). This is used for very slow I/O devices e.g. the UART
** Changed '''Command 06,0 '''
*** In ND-110, 'TBSTR' - Transmit Data Strobe command to the UART on the PCU card
*** In ND-120, 'spare'
** Changed '''Command 10''' SLOW (Command a "slow" microcycle)
*** In ND-110 a slow microcycle is 256ns
*** In ND-120 a slow microcycle is a minimum (no wait states) of 204.8ns

* Bits 37-41 ('''IDBS''' - Internal Data Bus Source)
** '''IDBS 34''' - In ND-110 this was 'JMPA', in ND-120 this is a 'spare'
** '''IDBS 36''' - In ND-110 this was a 'spare', in ND-120 this is 'PICMASK" (Read PIC mask register)
** '''IDBS 37''' - In ND-110 this was a 'spare', in ND-120 this is 'UART' (For reading from UART. See also command decode 5.x CEUART)

For more details check out the "ND-06.031.1 EN ND-110 and ND-120 Microprogrammer's Guide" document.[https://github.com/RonnyA/nd-120/blob/main/Code/Microcode/ND-06.031.1%20EN%20ND-110%20and%20ND-120%20Microprogrammer's%20Guide-Gandalf-OCR.pdf]

A scanned source of the the Microcode and a dump of the EPROM's from an ND-120/CX CPU version L is available
* '''Source listing and binary dump''' : [https://github.com/RonnyA/nd-120/tree/main/Code/Microcode Microcode Version L]

==Design documents==

* '''Root folder''': [https://github.com/RonnyA/nd-120 GitHub]

* '''All the original design documents''': [https://github.com/RonnyA/nd-120/tree/main/DesignDocuments Design Documents PDF files]

* '''Logisim Schematics re-created from design documents''': [https://github.com/RonnyA/nd-120/tree/main/Logisim Logisim CIRC files]

* '''Verilog code from converted Logisim Schemathics ''': [https://github.com/RonnyA/nd-120/tree/main/Verilog Verilog Files]

There is also a copy of the scanned design document PDF's at norsk-data.com:

* '''Circuit Diagrams''' [http://norsk-data.com/library/libhw/ND-06DEL-1-EN.pdf Access the Circuit Diagrams]
* '''Introduction to Hardware''' [http://norsk-data.com/library/libhw/ND-06DEL-2-EN.pdf View the Hardware Introduction]
* '''Design Documentation''' [http://norsk-data.com/library/libhw/ND-06DEL-3-EN.pdf Read the Design Documentation]
* '''Schematics''' [http://norsk-data.com/library/libhw/ND-06DEL-4-EN.pdf Explore the Schematics]

==Training videos==

* '''ND-120 - DELILAH - Hardware Introduction - Part 1 of 2''' [https://youtu.be/BzN33BQFg8g YouTube]
The ND-120 CPU was a complete reimplementation on an LSI chip (The so-called Delilah chip).
This is part 1 of 2 - with Lasse Bockelie from February 1987

* '''ND-120 - DELILAH - Hardware Introduction - Part 2 of 2''' [https://youtu.be/g3bIK9gkGyM YouTube]
The ND-120 CPU was a complete reimplementation on an LSI chip (The so-called Delilah chip).
This is part 2 of 2 - with Chris Cherrington from February 1987