FSB

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FSB
Description Subtract from floating accumulator
Format FSB <addr. mode> <disp.>
Code 104 0008
Affected T:=(ea) A=(ea+1) D=(ea+2)
Type User
Architecture ND-100, ND-110

FAD is an assembly instruction. The contents of the effective address and the following one or two locations are subtracted from the floating accumulator.

On 32-bit hardware only registers A and D are used, and two address locations instead of three. In this case, the A register is linked to (ea) and the D register to (ea+1).

References