3095 is the second ND-110 CPU board. The first version was numbered 3090. It contains the CPU, bus arbitration logic, memory control, cache memory and other subsystems, including the Real time clock and the I/O for the serial console.
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The ND-110 is an improvement over the ND-100 in a number of areas.
- Size. The CPU, the Memory Management System, cache memory and operator panel processor is combined on one single board.
- New technology. The CPU is constructed by a gate-array. The CPU concists of three VLSI gate arrays, RMIC, RMAC and BUFALU.
- New cache memory strategy. The first micro instruction word of a macroinstruction is stored in cache memory.
- Address arithmetic. Address arithmetic is performed in the RMAC gate array, not by the micro code as in ND-100.
- The interrupt system. Unlike the ND-100 CPU, the ND-110/CX CPU handles synchronous interrupts as traps., a bit like ND-500 does.
- The Control Store. The control store is based on fast read/write ram instead of prom. At power up the memory is initialised from two 8 kbyte EPROMs. The control store can be read or modified by program.
- Control logic and timing. Much of the control and timing logic have been moved into PAL chips. The main crystal oscillator is now a 39.3216 MHz oscillator. It is used for the nano-sequencer, the CPU-clock, the bus arbiter, the real time clock and the console UART. The nano-sequencer is a four bit state machine used for timing and control.
- Power consumption. The power consumption was reduced from 90 watts to 60.
Switches and indicators
The following switches and indicators are on the card
Location 28J - ALD edge switch Location 24J - self test lamp (green) Location 23J - running lamp (red) Location 22J - cache on lamp (red) Location 21J - cache on/off switch Location 8J - baud rate edge switch Location 7J - potentiometer
The A and B connectors are used for I/O, the C connector is used for the ND-100 Bus.
I/O Devices on the card
Console terminal interface
The console terminal interface is on the CPU board. It occupies the I/0 address address range 300 (octal) - 307 (octal). Addresses 301 (octal) and 304 (octal) are not used.
- address 300 (octal)
The read-data register contains the most recently received character.
- address 302 (octal)
The read-status register contains the current status of the input channel. The bits are assigned as follows:
- Bit 0: Set (= 1) if interrupt on data available.
- Bit 1: always zero.
- Bit 2: always zero.
- Bit 3: Set (= 1) if data is available. Note: bit 3 is never set when the CPU is in OPCOM mode.
- Bit 4: Set (= 1) if data is in error (one or more of bits 5-7 set).
- Bit 5: Set (= 1) if there was a framing error.
- Bit 6: Set (= 1) if there was a parity error.
- Bit 7: Set (= 1) if there was an overrun.
Bits 8-15 are always zero.
- address 303 (octal)
The read-control register is used to set the input channel parameters. Bits 0, 11, 12 and 13 and 14 are used. Unused bits should be set to zero. Note: The word length and parity settings also apply for the output channel.
- Bit 0: Set to 1 to enable interrupt when data is available.
- Bit 11 & 12: Bits 11 and 12 determine the word length. Parity, if used, adds 1 extra bit to the word 1ength.
|bit 11||bit 12||word length|
- Bit 13: Set (=> 1) for one stop bit. Reset (=> 0) for two stop bits (1.5 for 5-bit word length).
- Bit 14: Set (=> 1) to make the interface check parity. The word length will be increased by one when parity is being used.
- address 305 (octal)
Data written to the write-data register wi11 be sent to the output channel.
- address 306 (octal)
The write-status register contains the current status of the output channel. The bits are assigned as follows:
- Bit 0: Set (= 1) indicates that the interface will generate an interrupt when it is ready for transfer,
- Bit 3: Set (= 1) indicates that the transmitter is ready for transfer (data may be written).
Bits 1-2 and 4-5 are not used (always zero).
- address 307 (octal)
The write-control register is used to set the output channel parameters. Only bit 0 is used. Set the other bits to zero.
- Bit 0: Set (= 1) to generate interrupts when the device is ready for transfer (a new data word may be written to the write-data register).
The word length and parity (if used) are the same as set in the read-control register.
The real-time clock on the CPU board occupies device-register address range 10 (octal)-13 (octal). Address 10 (octal) is not used (returns 0).
clear real-time clock
- device-register address 11 (octal)
Writing to this address causes the next clock pulse to occur exactly 20 ms later. If this instruction is executed repeatedly, the counter will never be incremented, and no clock pulses will occur.
read clock status
- device-register address 12 (octal)
- Bit 0: Set (= 1) means that the clock will generate an interrupt when next clock pulse arrives.
- Bit 3: Set (= 1) means that the clock is ready for transfer (that is a clock pulse has occurred). Bits 1-2 and 4-15 are always zero.
set clock status
- device-register address 13 (octal)
- Bit 0: Set (=> 1) to enable interrupts when ready for transfer.
- Bit 13: Set (=> 1) to clear the ready for transfer bit in the clock status register.
- TRA CS - Reads 16 control storage bits into the A-register. The X-register contains the store address.
- TRR CS - Writes the A-register into 16 control store bits. The X-register contains the control store address.
- TRR CILP - Cache inhibit individual page.
- VERSN - Reads version numbers of print and micro program.
- SETPT - Set page tables.
- CLEPT - Clear page tables.
- CLNREENT - Clear non re-entrant pages.
- CHREENTPAGES - Change page tables.
- CLEPU - Clear page tables and collect PGU information.
- WGLOB - Initialize global pointers.
- RGLOB - Examine global pointers.
- INSPL - Insert page in page list.
- REMPL - Remove page from page list.
- CNREK - Clear non re-entrant pages.
- CLPT - Clear segment from page tables.
- ENPT - Enter segment in page tables.
- REPT - Enter re-entrant segment in page tables.
- LBIT - Load single bit accumulator (K) with logical memory bit.
- SBITP - Store single bit accumulator (K) in a physical memory bit.
- LBYTP - Load the A register with a single byte from physical memory.
- SBYTP - Store single byte in physical memory.
- TSETP - Test and set a physical memory word.
- RDUSP - Read a physical memory word without using cache.
- LASB - Load the A register with the contents of the segment-table bank (STBNK).
- SASB - Store the A register contents in the STBNK.
- LACB - Load the A register with the contents of the core map-table bank (CMBNK).
- SACB - Store the A register contents in the CMBNK.
- LXSB - Load the X register with the contents of the STBNK.
- LXCB - Load the X register with the contents of the CMBNK.
- SZSB - Store zero in the STBNK.
- SZCB - Store zero in the CMBNK.