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Description Multiply floating accumulator
Format FMU <addr. mode> <disp.>
Code 110 0008
Affected T A D, TG
Type User
Architecture ND-100, ND-110

FMU is an assembly instruction. The contents of the effective address and the following one or two locations are multiplied with the floating accumulator with the result in the floating accumulator (T A D).

On 32-bit floating point hardware only registers A and D are used, and two address locations instead of three (ea and ea+1).

Flags affected

The rounding indicator for floating point operations (TG, sometimes called just G) may be set by this instruction.