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- == ND-100 CPU registers and organisation == === Register File === The ND-100 CPU has a register file of 256 registers, organised as 16 registers ...3 KB (404 words) - 00:17, 18 January 2009
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- == ND-100 CPU registers and organisation == === Register File === The ND-100 CPU has a register file of 256 registers, organised as 16 registers ...3 KB (404 words) - 00:17, 18 January 2009
- [[File:NorskData-1008-II-Interrupt Registers-ComponentSide.jpg|thumb|left]] ... [[File:NorskData-1008-II-Interrupt Registers-SolderSide.jpg|thumb|left]] ...319 bytes (36 words) - 08:13, 7 September 2022
- STF is an assembly instruction. The content of the floating accumulator (T, A and D registers) is stored in three consecutive memory locations ...1 KB (170 words) - 14:24, 8 August 2009
- The source operand is defined by the A and D registers. The destination ... the operands are defined. Source: A and D registers. Destination: X and T registers. ...2 KB (246 words) - 13:56, 26 July 2010
- RMPY is an assembly instruction. The source and destination registers are multiplied. The result is a 32-bit signed integer left in the A and ...669 bytes (88 words) - 14:24, 15 July 2012
- into the floating accumulator, i.e. T, A and D registers. The instruction always load the three registers, even in CPUs with the 32-bit floating point ...1 KB (172 words) - 14:29, 30 June 2010
- Effective address (abbr. ea) is the address calculated from the contents of various registers and/or a displacement. == See also == ...259 bytes (29 words) - 15:32, 3 April 2009
- LBYT is an assembly instruction. A byte specified by the T and X registers is loaded into the A register bits 0-7, with the A register bits 8 ...851 bytes (137 words) - 16:06, 24 July 2010
- The source operand is defined by the A and D registers. The destination ... the operands are defined. Source: A and D registers. Destination: X and T registers. ...2 KB (361 words) - 16:26, 16 May 2011
- SBYT is an assembly instruction. The byte in the A register bits 0-7 is stored in one half of the effective address defined by the T and X registers ...915 bytes (147 words) - 16:51, 24 July 2010
- 100000-100777 System control registers 101000-107777 Reserved ... System registers : Some system control registers are controlled via ...2 KB (261 words) - 21:45, 23 July 2014
- BFILL is an assembly instruction. A byte operand memory area defined by the X and T registers is filled with the value of the right-most byte ...2 KB (336 words) - 13:19, 26 July 2010
- to examine or modify memory locations and registers. may be ... ; REGISTERS : all registers on all hardware interrupt levels may be ...3 KB (472 words) - 14:24, 2 October 2017
- PCB 1062 is the Status PCB for the NORD-10 CPU. It has all the status registers of the CPU == Pictures == {| class="wikitable" ...315 bytes (41 words) - 13:37, 7 September 2022
- PCB 1002 is the registers PCB for the ND-10 CPU. The ND-10 CPU uses four of this card. == Pictures == {| class="wikitable" ...319 bytes (40 words) - 07:49, 7 September 2022
- This means that all I/O device registers which need to be loaded from ... octal) are used to specify system control registers which have to be accessed ...3 KB (410 words) - 08:39, 21 March 2013
- This means that all I/O device registers which need to be loaded from ... The IOX instruction can address a total of 2048 registers, i.e. addresses ...4 KB (550 words) - 14:02, 1 February 2019
- on the specific monitor call, various registers may be loaded with call-specific values before the MON instruction is called, and return values ...2 KB (374 words) - 13:31, 7 August 2010
- On 32-bit floating point hardware only registers A and D are used, and two address locations instead of three. == Flags affected == ...861 bytes (111 words) - 09:58, 1 July 2010
- On 32-bit floating point hardware only registers A and D are used, and two address locations instead of three. == Flags affected == ...847 bytes (111 words) - 10:01, 1 July 2010