Difference between revisions of "3002"

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==== RTC IOX register map ====
 
==== RTC IOX register map ====
  
IOX 10:
+
;IOX 10
Returns 0 in A register, no other effect.
+
:Returns 0 in A register, no other effect.
  
IOX 11:
+
;IOX 11
Clears real time counter. This instruction will cause the
+
:Clears real time counter. This instruction will cause the next clock pulse to occur exactly 20 ms later.
next clock pulse to occur exactly 20 ms later.
+
:If executed often enough it will stop the real-time counter from incrementing. This could affect operators communicating via the console.
If executed often enough it will stop the real-time counter
+
from incrementing. This could affect operators communicating
+
via the console.
+
  
IOX 12:
+
;IOX 12
Read real-time clock status.
+
:Read real-time clock status.
  Bit 0=1 : An interrupt will be generated at the next clock pulse.
+
: Bit 0=1 : An interrupt will be generated at the next clock pulse.
  Bit 3=1 : A clock pulse has occurred.
+
: Bit 3=1 : A clock pulse has occurred.
  Bit 1-2 and 4-15 is always zero.
+
: Bit 1-2 and 4-15 is always zero.
  
IOX 13:
+
;IOX 13
Set real-time clock status.
+
:Set real-time clock status.
  Bit 0=1 : Enable interrupt on next clock pulse.
+
: Bit 0=1 : Enable interrupt on next clock pulse.
  Bit 13=1 : Set bit 3 to zero in the real-time clock status word.
+
: Bit 13=1 : Set bit 3 to zero in the real-time clock status word.
  
 
=== Console ===
 
=== Console ===
 
 
The console could be disabled by removing a strap.
 
The console could be disabled by removing a strap.
  
 
==== Console IOX register map ====
 
==== Console IOX register map ====
  
IOX 300:
+
;IOX 300
Read input data (according to input control word setting).
+
:Read input data (according to input control word setting). The last character is transferred to the A register. The data available signal is reset if [[MOPC]] is not active.
The last character is transferred to the A register. The
+
 
data available signal is reset if [[MOPC]] is not active.
+
;IOX 301
 +
:No operation.
  
IOX 301:
+
;IOX 302
No operation.
+
:Read input status
 +
: Bit 0=1 : Interrupt on "Data available" enabled.
 +
: Bit 3=1 : Data available. (Never set when [[MOPC]] is active.)
 +
: Bit 4=1 :
 +
: Bit 5=1 :
 +
: Bit 6=1 :
 +
: Bit 7=1 :
  
IOX 302:
+
;IOX 303
Read input status
+
:Set input control
  Bit 0=1 : Interrupt on "Data available" enabled.
+
: Bit 0=1 : Enable interrupt on "Data available".
  Bit 3=1 : Data available. (Never set when [[MOPC]] is active.)
+
: Bit 11=0, bit 12=0 : 8 bit data.
  Bit 4=1 :  
+
: Bit 11=1, bit 12=0 : 7 bit data.
  Bit 5=1 :  
+
: Bit 11=0, bit 12=1 : 6 bit data.
  Bit 6=1 :  
+
: Bit 11=1, bit 12=1 : 5 bit data.
  Bit 7=1 :  
+
: Bit 13=0 : 2 stop bits (1.5 stop bits for 5 bit data).
 +
: Bit 13=1 : 1 stop bit.
 +
: Bit 14=0 : No parity.
 +
: Bit 14=1 : Parity bit added to data.
  
IOX 303:
+
;IOX 304
Set input control
+
:Returns 0 in A register, no other effect.
  Bit 0=1 : Enable interrupt on "Data available".
+
  Bit 11=0, bit 12=0 : 8 bit data.
+
  Bit 11=1, bit 12=0 : 7 bit data.
+
  Bit 11=0, bit 12=1 : 6 bit data.
+
  Bit 11=1, bit 12=1 : 5 bit data.
+
  Bit 13=0 : 2 stop bits (1.5 stop bits for 5 bit data).
+
  Bit 13=1 : 1 stop bit.
+
  Bit 14=0 : No parity.
+
  Bit 14=1 : Parity bit added to data.
+
  
IOX 304:
+
;IOX 305
Returns 0 in A register, no other effect.
+
:Write output data (according to input control word setting).
  
IOX 305:
+
;IOX 306
Write output data (according to input control word setting).
+
:Read output status.
 +
: Bit 0=1 : Interrupt on "Ready for transfer" is enabled.
 +
: Bit 3=1 : Ready for transfer.
 +
: Bit 1-2 and 4-5 are always zero ''(should probable be 1-2 and 4-15, an error in the documentation)''.
  
IOX 306:
+
;IOX 307
Read output status.
+
:Set output control.
  Bit 0=1 : Interrupt on "Ready for transfer" is enabled.
+
: Bit 0=1 : Enable interrupt on "Ready to transfer"
  Bit 3=1 : Ready for transfer.
+
  Bit 1-2 and 4-5 are always zero.
+
    (should probable be 1-2 and 4-15, an error in the documentation)
+
  
IOX 307:
+
=== Notes ===
Set output control.
+
There is some strange wordings in the manual but I guess that there is no interrupts or reset of the data ready status bit when MOPC is running.
  Bit 0=1 : Enable interrupt on "Ready to transfer"
+
  
'''Notes''' :
 
There is some strange wordings in the manual but I guess that there is
 
no interrupts or reset of the data ready status bit when MOPC is running.
 
  
 
== Reference ==
 
== Reference ==

Revision as of 09:39, 12 November 2008

ND 100 CPU board

3002 is the ND-100 CPU board. It contains the CPU, bus arbitration logic, memory control and other subsystems. It also have the Real time clock and the I/O for the serial console.

There are schematics of the CPU in the Norsk Data Document ND–06.016 ND-100 INPUT/OUTPUT SYSTEM (ND-06.016.01).

Description of MOPC

Main article: MOPC

MOPC is the name of the Microprogrammed OPerators Communication, a program stored in the micro code of the CPU. It can be used for low level testing of the hardware. Whenever the MOPC is active it is communicating via the console connected to the current loop connection on the CPU card. MOPC contains functions for examination of the memory, dumping registers, changing content in registers or memory, controlling breakpoints, bootstrap loading and other things.

I/O devices on the CPU board

The CPU board is equipped with two I/O devices, the real time clock and the system console.

RTC

RTC is the Real-Time Clock. It is a system that could generate interrupts on a 20 ms basis.

RTC IOX register map

IOX 10
Returns 0 in A register, no other effect.
IOX 11
Clears real time counter. This instruction will cause the next clock pulse to occur exactly 20 ms later.
If executed often enough it will stop the real-time counter from incrementing. This could affect operators communicating via the console.
IOX 12
Read real-time clock status.
Bit 0=1 : An interrupt will be generated at the next clock pulse.
Bit 3=1 : A clock pulse has occurred.
Bit 1-2 and 4-15 is always zero.
IOX 13
Set real-time clock status.
Bit 0=1 : Enable interrupt on next clock pulse.
Bit 13=1 : Set bit 3 to zero in the real-time clock status word.

Console

The console could be disabled by removing a strap.

Console IOX register map

IOX 300
Read input data (according to input control word setting). The last character is transferred to the A register. The data available signal is reset if MOPC is not active.
IOX 301
No operation.
IOX 302
Read input status
Bit 0=1 : Interrupt on "Data available" enabled.
Bit 3=1 : Data available. (Never set when MOPC is active.)
Bit 4=1 :
Bit 5=1 :
Bit 6=1 :
Bit 7=1 :
IOX 303
Set input control
Bit 0=1 : Enable interrupt on "Data available".
Bit 11=0, bit 12=0 : 8 bit data.
Bit 11=1, bit 12=0 : 7 bit data.
Bit 11=0, bit 12=1 : 6 bit data.
Bit 11=1, bit 12=1 : 5 bit data.
Bit 13=0 : 2 stop bits (1.5 stop bits for 5 bit data).
Bit 13=1 : 1 stop bit.
Bit 14=0 : No parity.
Bit 14=1 : Parity bit added to data.
IOX 304
Returns 0 in A register, no other effect.
IOX 305
Write output data (according to input control word setting).
IOX 306
Read output status.
Bit 0=1 : Interrupt on "Ready for transfer" is enabled.
Bit 3=1 : Ready for transfer.
Bit 1-2 and 4-5 are always zero (should probable be 1-2 and 4-15, an error in the documentation).
IOX 307
Set output control.
Bit 0=1 : Enable interrupt on "Ready to transfer"

Notes

There is some strange wordings in the manual but I guess that there is no interrupts or reset of the data ready status bit when MOPC is running.


Reference