FDV

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FDV
Description Divide floating accumulator
Format FDV <addr. mode> <disp.>
Code 114 0008
Affected T A D, Z, TG
Type User
Architecture ND-100, ND-110

FDV is an assembly instruction. The contents of the floating accumulator is divided by the floating word in the effective address and the following one or two locations, with the result in the floating accumulator (T A D).

If division by zero is attempted the error indicator Z is set to one.

On 32-bit floating point hardware only registers A and D are used, and two address locations instead of three (ea and ea+1).

Flags affected

The rounding indicator for floating point operations (TG, sometimes called just G) may be set by this instruction.
The error indicator (Z) is set if division by zero is attempted. The flag may be tested by a following BSKP instruction.

References