ND-110 CPU

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Introduction

The ND-110 is an improvement over the ND-100 in a number of areas.

  • Size. The CPU, the Memory Management System, cache memory and operator panel processor is combined on one single board.
  • New technology. The CPU is constructed by a gate-array. The CPU concists of three VLSI gate arrays, RMIC, RMAC and BUFALU. The ND-110 CPU is also making extensive usage of programmable logic.
  • New cache memory strategy. The first micro instruction word of a macroinstruction is stored in cache memory.
  • Address arithmetic. Address arithmetic is performed in the RMAC gate array, not by the micro code as in ND-100.
  • The interrupt system. Unlike the ND-100 CPU, the ND-110 (and ND-100/CX) CPU handles synchronous interrupts as traps, in a similar way as ND-500 does.[1]
  • The Control Store. The control store is based on fast read/write RAM instead of PROM. At power up the memory is initialised from two 8 kbyte EPROMs. The control store can be read or modified by program.
  • Control logic and timing. Much of the control and timing logic have been moved into PAL chips. The main crystal oscillator is now a 39.3216 MHz oscillator. It is used for the nano-sequencer, the CPU-clock, the bus arbiter, the real time clock and the console UART. The nano-sequencer is a four bit state machine used for timing and control.
  • Power consumption. The power consumption was reduced from 90 watts to 60.[citation needed]

The VLSI chips

  • The Micro Instruction Controller, the MIC - also known as RMIC, for "Rask MIC" ("Speedy MIC"). It replaced three 74S482 sequencers and about 30 other ICs.
  • The Arithmetical and Logical Unit gate array (ALU, also known as the "BUFALU"). Replaced four Am2901 bit-slice processors, and some additional registers like the data bus register the general purpose register, and the internal register block.
  • The Micro Address Controller (The MAC, also called RMAC, for "Rask MAC" ("Speedy MAC"). It implemented hardware address arithmetic, which in the ND-100 had been done in microcode.

Cache memory details

In addition to the macro-instruction cache memory also found in the ND-100, the ND-110 had a unique implementation of cache memory on the micro-instruction level. The step known as mapping in the ND-100 was then avoided because the first micro-instruction word of a macro-instruction was written into the control store cache.


Versions

The ND-110 CPU comes in two versions. A standard version and a fast version. Depending on application the ND-110/CX is 1.5 to 3.5 times faster than ND-110. Both versions comes with memory management, a new type of cache memory and the commercial extended instruction set as standard.[2]

ND-110

This is the standard ND-110 version. It has the same performance as the ND-100/CX. It has a 1k word instruction cache and executes with 0.32 Whetstone MIPS.

ND-110/CX

This is the fast version of the ND-110 CPU. It is 1.5-3.5 faster than the standard version. It has a 4k word instruction and data cache and executes with 0.55 Whetstone MIPS.

Print versions

  • 3090 An early version of the CPU with two different print release versions (C, K)
  • 3095 A later version of the CPU, only known print release version is B.

New instructions

  • TRA CS - Reads 16 control storage bits into the A-register. The X-register contains the store address.
  • TRR CS - Writes the A-register into 16 control store bits. The X-register contains the control store address.
  • TRR CILP - Cache inhibit individual page.
  • VERSN - Reads version numbers of print and micro program.
  • SETPT - Set page tables.
  • CLEPT - Clear page tables.
  • CLNREENT - Clear non re-entrant pages.
  • CHREENTPAGES - Change page tables.
  • CLEPU - Clear page tables and collect PGU information.
  • WGLOB - Initialize global pointers.
  • RGLOB - Examine global pointers.
  • INSPL - Insert page in page list.
  • REMPL - Remove page from page list.
  • CNREK - Clear non re-entrant pages.
  • CLPT - Clear segment from page tables.
  • ENPT - Enter segment in page tables.
  • REPT - Enter re-entrant segment in page tables.
  • LBIT - Load single bit accumulator (K) with logical memory bit.
  • SBITP - Store single bit accumulator (K) in a physical memory bit.
  • LBYTP - Load the A register with a single byte from physical memory.
  • SBYTP - Store single byte in physical memory.
  • TSETP - Test and set a physical memory word.
  • RDUSP - Read a physical memory word without using cache.
  • LASB - Load the A register with the contents of the segment-table bank (STBNK).
  • SASB - Store the A register contents in the STBNK.
  • LACB - Load the A register with the contents of the core map-table bank (CMBNK).
  • SACB - Store the A register contents in the CMBNK.
  • LXSB - Load the X register with the contents of the STBNK.
  • LXCB - Load the X register with the contents of the CMBNK.
  • SZSB - Store zero in the STBNK.
  • SZCB - Store zero in the CMBNK.

Microcode format

The ND-110/CX microcode format is described in Norsk Data Document ND–06.026 ND-110 Functional Description (ND-06.026.01 rev A page 235).

There is a surviving list of the microcode version K [3] in Telemuseums storage in Fetsund. It's not easy to read and almost 200 pages of code. Interestingly enough, there are some mention of SINTRAN IV in the code.

Reference and Sources

  1. Norsk Data Document ND–06.026 ND-110 Functional Description (ND-06.026.01 EN) page 191
  2. Norsk Data Document ND–06.026 ND-110 Functional Description (ND-06.026.01 EN) page 3
  3. MICROPROGRAMLISTNING FOR ND-110_32 BIT VERSION K