MPM-5

Full Name

Multiport Memory 5

Abbreviation

MPM-5

Introduced

June 1984 (technical description published)

Purpose

Multi-processor shared memory system

Used In

ND-100, ND-500, ND-500-II systems

MPM-5 (Multiport Memory 5) was Norsk Data's shared memory system that enabled multiple processors (ND-100, ND-500, ND-500-II) to access a common pool of memory simultaneously. It was the foundation for multi-processor configurations before the ND-5000 era introduced OCTOBUS and MFbus.

Overview

MPM-5 provided a multiport memory architecture that allowed:

• Multiple processors to read/write shared data structures
• DMA controllers to access memory independently
• Real-time coordination between CPUs via shared memory synchronization
• System configurations from 1 to 4 processors

The system consisted of three main hardware modules:

• Twin 16-Bit Port Module — Entry point for each CPU into the memory bank
• Dynamic RAM Module — Physical storage (up to 16MW per bank)
• Line Driver Module — Inter-bank signal distribution for global memory access

Architecture

Memory Organization

Bank Structure

Each MPM-5 bank = 64KW (128KB) addressable by 16-bit register

Maximum 256 banks = 16MW (32MB) total addressing

Addressing

Local access — Within single bank (64KW per port)

Global access — Through line driver to other banks

Address decoding via dual RAMs (LOCAL and GLOBAL paths)

Modules

Twin 16-Bit Port (PCB 5152 or 5155)

2 × 16-bit width (compatible with 16-bit and 32-bit channels)

Accepts up to 29 address bits (32-bit word addressing)

Port control registers for configuration

Master/slave control for arbitration

Dynamic RAM (PCB)

Variable capacity configurations

Error correction and detection

Error logging and suppression registers

Memory test and diagnostic support

Line Driver (PCB 5166 or variant)

Differential signaling between banks

Address and data distribution

Control signal buffering

Global memory coordination

Addressing Modes

Interleave Types

16-bit interleave (ND-100 mode)

32-bit interleave (ND-500 mode for 64-bit cache systems)

32-bit non-interleave

Configurable via port control register

Address Windows

Define memory regions accessible per port

Separate decoding for LOCAL (within-bank) vs GLOBAL (cross-bank)

Address conversion tables (5152/5155 specific)

ALLOW bit on 5155 for cache-width selection

Integration with Computers

ND-100 Systems

ND-100 CPUs could be extended with MPM-5 for:

• Multi-processor real-time coordination
• I/O processor + compute processor configurations
• Shared program/data memory access

Integration described in ND-06.015 (ND-100 Functional Description)

ND-500 Systems

ND-500 coprocessors used MPM-5 for:

• Communication with ND-100 I/O processor
• Shared memory for message passing (pre-NUCLEUS)
• Multiport access from up to 4 ND-500 CPUs
• DMA controller data transfer coordination

Integration described in ND-05.011 (ND-500 Hardware Description)

ND-500-II Systems

ND-500-II retained MPM-5 for:

• NUCLEUS kernel data structures
• Port and message queues (shared with ND-100)
• OCTOBUS coordination via line driver
• Backward compatibility with ND-500 code

ND-5000 Transition

ND-5000 systems replaced MPM-5 with:

• MFbus (Multifunction Bus) — successor technology
• OCTOBUS — native serial signaling (not via line drivers)
• Improved performance and integrated architecture

Control and Test Registers

MPM-5 ports featured extensive register sets:

Master Control Register

System-wide configuration and control

Interleave type selection

Cache width settings (32-bit vs 64-bit)

Port Control Register

Per-port configuration

Address window setup

Base address and limit configuration

Master/Port Status Registers

Status flags and error indicators

Memory test results

Port state monitoring

Test/Debug Support

Test request registers

Test data and address registers

Memory display/dump capability

Error memory access

Programming Guide

Common Operations

CONFIGURATE-SLOT: Set up memory slots and window boundaries LIST-CONFIGURATION: Display current memory configuration MEMORY-TEST: Run diagnostic memory tests MEMORY-DUMP: Examine memory contents INVESTIGATE-BANK: Analyze bank status and limits AUTOINITIATE-BANK: Auto-initialize new banks

Error Handling

• Error logging to memory with address/data capture
• Error table suppression for known failures
• Interrupt-driven error notification
• Error investigator diagnostics

System Startup

Cold Start: Full initialization of all banks Warm Start: Re-initialization after restart System Expansion: Adding banks or ports dynamically Termination: Graceful shutdown procedures

Multiport Memory Evolution

Generation	Memory Unit	Used In	Status
MPM-3	16KW per module	Early ND-100	Obsolete
MPM-4	32KW per module	Mid ND-100 era	Obsolete
MPM-5	64KW banks, 256 banks max	ND-100, ND-500, ND-500-II	Last of the classic generation
MFbus	(successor)	ND-5000	Modern replacement

Introduction to multiport concepts documented in ND-10.006 (Multiport Memory Channel Specifications)

Internal bus architecture documented in ND-10.005 (Multiport Memory 5 Bus Description)

Synchronization Primitives

MPM-5 provided low-level synchronization for multi-processor systems:

• Atomic test-and-set operations for semaphores
• Mailbox mechanisms for inter-CPU messages
• Interrupt signaling via shared flags
• TSET instructions for mutual exclusion (ND-500/ND-100)

Before NUCLEUS formalized message passing, MPM-5 was the foundation for all ND-500 / ND-100 inter-processor communication.

See Also

• ND-100 — Primary processor using MPM-5
• ND-500 — 32-bit coprocessor for MPM-5
• ND-500-II — ND-500 with OCTOBUS using MPM-5
• NUCLEUS — Message-passing runtime built on MPM-5 (ND-500-II/ND-5000)
• MFbus — Modern successor to MPM-5 (ND-5000)
• OCTOBUS — Serial signaling complement to MPM-5
• Multiport Memory — General concept and alternatives

Product Numbers

• Manual: ND-10.004.01 (MPM-5 Technical Description, June 1984)
• Related specs: ND-10.005 (Bus Description), ND-10.006 (Channel Specifications)

External Links

• ND-10.004.01 MPM-5 Technical Description
• ND-10.005 Multiport Memory 5 Bus Description
• ND-10.006 Multiport Memory Channel Specifications