LWCS

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LWCS
Description Load Writeable Control Store
Format LWCS
Code 143 5008
Affected
Type Privileged
Architecture NORD-10, ND-100 (ND-110)

LWCS is an instruction on the ND platform. It loads the contents of main memory locations with addresses from 15K to 16K into the optional 256 word by 64 bit RAM writeable control store.

Microprogram addresses from 74008 to 77778 will then be accessible. When the instruction is finished, all microprogram addresses are legal and illegal instruct. ROM out of range interrupt will never occur.

The LWCS-instruction must always be performed before executing instructions using microaddresses in the range 4000-7777. This is necessary even if no writeable control store option is installed. The microinstructions from 4000 to 7777 are only used by instructions described in the chapters on the CE or CX options.

No-operation

LWCS is a no-operation in the ND-110. The ND-110 is software compatible but not microcode compatible and writing to the writable control store has no meaning in the ND-110. A no-operation is executed so that programs written for the ND-100 and NORD-10 can continue.

For the ND-110 series of CPUs see instructions TRA CS and TRR CS for access to the control store.

References