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- 072415 X:=PERR; *TRR PCR 072417 X.SN1=:D ... 072421 "NMPIT+ADPIT+LV14B+ERNG2"; *TRR PCR ...3 KB (493 words) - 07:45, 26 May 2016
- on the memory module so the microcode converts the TRR instruction to an IOXT 100115 == ND IO interrupts == If the IO address is to a non-existing ...2 KB (261 words) - 21:45, 23 July 2014
- * TRR CS - Writes the A-register into 16 control store bits. The X ... * TRR CILP - Cache inhibit individual page. * VERSN - Reads version ...6 KB (903 words) - 11:03, 28 April 2019
- located on the memory modules. ECCR is loaded by the TRR instruction. However, since ECCR is accessed via the ND-100 bus, the microprogram performs the ...3 KB (410 words) - 08:39, 21 March 2013
- * TRR CS - Writes the A-register into 16 control store bits. The X ... * TRR CILP - Cache inhibit individual page. * VERSN - Reads version ...9 KB (1,367 words) - 14:48, 2 June 2023
- and PANC and the privileged instructions TRA 0 and TRR 0. == PANC - Panel Control Register == The Panel Control Register is used to send commands ...4 KB (658 words) - 13:27, 27 April 2018
- | 150100 || TRR |- | 150200 || MCL |- | 150300 || MST |- | 150400 || OPCOM |- | 150401 || IOF |- | 150402 || ION |- | 150404 || POF ...4 KB (413 words) - 21:46, 18 May 2019
- * TRR – Transfer to register ==== Inter-level Instructions ==== * IRR – Inter Register Read * IRW – Inter Register Write === Register Operations ...8 KB (1,031 words) - 13:25, 8 February 2012
- by means of the BOP instruction or by the TRA or TRR sub-instructions where all flip-flops must be transferred to and from the A-register. ...9 KB (1,292 words) - 09:43, 25 July 2016
- by means of the BOP instruction or by the TRA or TRR subinstructions where all flip-flops must be transferred to and from the A-register. ...12 KB (1,810 words) - 15:26, 5 August 2020